| Description: CCD Storage clock pattern. CCD Storage clock patterns during a storage to horizontal register transfer. There are 8 bit periods per storage clock cycle. The CS2H_CCD determines the high to low ratio incremented each VFREQCSR count cycle. |
| Namespace Id: orex | Steward: sbn | Class Name: OCAMS_Instrument_Attributes | Type: ASCII_Integer |
| Minimum Value: -9223372036854775808 | Maximum Value: 9223372036854775807 | Minimum Characters: None | Maximum Characters: None |
| Unit of Measure Type: None | Default Unit Id: None | Attribute Concept: None | Conceptual Domain: INTEGER |
| Status: Active | Nillable: false | Pattern: None |
| Permissible Value(s) | No Values | |